`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/20 15:32:27
// Design Name: 
// Module Name: moore_top_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

/*
input rst_n_i,
    input clk_i,
    input set_i,
    input [7:0] data_i,
    output reg detect_o
*/

module moore_top_sim();
    reg clk_i = 1'b0;
    reg rst_i = 1'b0;
    reg set_i = 1'b0;
    reg [7:0] data_i = 1'b0;
    wire detect_o;
    
    moore_top UUT(.rst_i(rst_i), .clk_i(clk_i), .set_i(set_i), .data_i(data_i), .detect_o(detect_o));
    
    always #1 begin clk_i = ~clk_i; end
    
    initial begin
        data_i = 8'b0001_0101; set_i = 'b1; #14 set_i = 'b0;  // FIRST BYTE READ IN
        #185 set_i = 1; data_i = 8'b1100_0000; #20 set_i = 'b0;   // SECOND BYTE READ IN
        #185 rst_i = 'b1;  #20 rst_i = 'b0;  // RESET
        data_i = 8'b0001_0101; set_i = 'b1; #14 set_i = 'b0;  // FIRST BYTE READ IN
        #185 rst_i = 'b1;  #20 rst_i = 'b0;  // RESET
        #185 set_i = 1; data_i = 8'b1100_0000; #20 set_i = 'b0;   // SECOND BYTE READ IN
        #170 $stop;
    end
endmodule
